View ADN4693EBRZ_5230639.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3.3 v, 200 mbps, half- and full-duplex, high speed m-lvds transceivers data sheet adn4691e / adn4693e / adn4696e / adn4697e rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011C2012 analog devices, inc. all rights reserved. features multipoint lvds transceivers (low voltage differential signaling driver and receiver pairs) switching rate: 200 mbps (100 mhz) supported bus loads: 30 to 55 choice of 2 receiver types type 1 ( adn4691e / adn4693e ): hysteresis of 25 mv type 2 ( adn4696e / adn4697e ): threshold offset of 100 mv for open-circuit and bus-idle fail-safe conforms to tia/eia-899 standard for m-lvds glitch-free power-up/power-down on m-lvds bus controlled transition times on driver output common-mode range: ?1 v to +3.4 v, allowing communication with 2 v of ground noise driver outputs high-z when disabled or powered off enhanced esd protection on bus pins 15 kv hbm (human body model), air discharge 8 kv hbm (human body model), contact discharge 10 kv iec 61000-4-2, air discharge 8 kv iec 61000-4-2, contact discharge operating temperature range: ?40c to +85c available in 8-lead ( adn4691e / adn4696e ) and 14-lead ( adn4693e / adn4697e ) soic packages applications backplane and cable multipoint data transmission multipoint clock distribution low power, high speed alternative to shorter rs-485 links networking and wireless base station infrastructure functional block diagrams adn4691e/ adn4696e v cc gnd ro r d re de a b di 10355-001 figure 1. adn4693e/ adn4697e v cc gnd ro r d re de di 10355-002 a b z y figure 2. general description the adn4691e / adn4693e / adn4696e / adn4697e are multipoint, low voltage differential signaling (m-lvds) transceivers (driver and receiver pairs) that can operate at up to 200 mbps (100 mhz). the receivers detect the bus state with a differential input of as little as 50 mv over a common-mode voltage range of ?1 v to +3.4 v. esd protection of up to 15 kv is implemented on the bus pins. the parts adhere to the tia/eia-899 standard for m-lvds and complement tia/eia- 644 lvds devices with additional multipoint capabilities. the adn4691e / adn4693e are type 1 receivers with 25 mv of hysteresis, so that slow-changing signals or loss of input does not lead to output oscillations. the adn4696e / adn4697e are type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe). the parts are available as half-duplex in an 8-lead soic package (the adn4691e / adn4696e ) or as full-duplex in a 14-lead soic package (the adn4693e / adn4697e ). a selection table for the adn469xe parts is shown in table 1 . table 1. adn469xe selection table part no. receiver data rate soic duplex adn4690e type 1 100 mbps 8-lead half adn4691e type 1 200 mbps 8-lead half adn4692e type 1 100 mbps 14-lead full adn4693e type 1 200 mbps 14-lead full adn4694e type 2 100 mbps 8-lead half adn4695e type 2 100 mbps 14-lead full adn4696e type 2 200 mbps 8-lead half adn4697e type 2 200 mbps 14-lead full
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagrams............................................................. 1 ? general description ......................................................................... 1 ? revision history ........................................................................... 2 ? specifications..................................................................................... 3 ? receiver input threshold test voltages .................................... 4 ? timing specifications .................................................................. 5 ? absolute maximum ratings............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution.................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? test circuits and switching characteristics................................ 11 ? driver voltage and current measurements............................ 11 ? driver timing measurements .................................................. 12 ? receiver timing measurements............................................... 13 ? theory of operation ...................................................................... 14 ? half-duplex/full-duplex operation....................................... 14 ? three-state bus connection..................................................... 14 ? truth tables................................................................................. 14 ? glitch-free power-up/power-down....................................... 15 ? fault conditions ......................................................................... 15 ? receiver input thresholds/fail-safe........................................ 15 ? applications information .............................................................. 16 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 17 ? revision history 3/12rev. 0 to rev. a added adn4691e and adn4693e ................................. universal changes to features section, general description section, and table 1..........................................................................................1 added type 1 receiver parameters, table 2 ..................................3 added table 3, renumbered sequentially .....................................4 added type 1 receiver parameters, table 5 ..................................5 added table 7.....................................................................................6 changes to table 8.............................................................................7 changes to figure 33.......................................................................13 added table 12 ................................................................................14 changes to receiver input thresholds/fail-safe section and figure 36....................................................................................15 changes to ordering guide ...........................................................17 12/11revision 0: initial version
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 3 of 20 specifications v cc = 3.0 v to 3.6 v; r l = 50 ; t a = t min to t max , unless otherwise noted. 1 table 2. parameter symbol min typ max unit test conditions/comments driver differential outputs differential output voltage magnitude |v od | 480 650 mv see figure 19 ?|v od | for complementary output states ?|v od | ?50 +50 mv see figure 19 common-mode output voltage (steady state) v oc(ss) 0.8 1.2 v see figure 20 , figure 23 v oc(ss) for complementary output states v oc(ss) ?50 +50 mv see figure 20 , figure 23 peak-to-peak v oc v oc(pp) 150 mv see figure 20 , figure 23 maximum steady-state open-circuit output voltage v a(o) , v b(o) , v y(o) , or v z(o) 0 2.4 v see figure 21 voltage overshoot low to high v ph 1.2v ss v see figure 24 , figure 27 high to low v pl ?0.2v ss v see figure 24 , figure 27 output current short circuit |i os | 24 ma see figure 22 high impedance state, driver only i oz ?15 +10 a C1.4 v (v y or v z ) 3.8 v, other output = 1.2 v power off i o(off) ?10 +10 a C1.4 v (v y or v z ) 3.8 v, other output = 1.2 v, 0 v v cc 1.5 v output capacitance c y or c z 3 pf v i = 0.4 sin(30e 6 t) v + 0.5 v, 2 other output = 1.2 v, de = 0 v differential output capacitance c yz 2.5 pf v ab = 0.4 sin(30e 6 t) v, 2 de = 0 v output capacitance balance (c y /c z ) c y/z 0.99 1.01 logic inputs (di, de) input high voltage v ih 2 v cc v input low voltage v il gnd 0.8 v input high current i ih 0 10 a v ih = 2 v input low current i il 0 10 a v il = 0.8 v receiver differential inputs differential input threshold voltage type 1 receiver ( adn4691e , adn4693e ) v th ?50 +50 mv see table 3 , figure 36 type 2 receiver ( adn4696e , adn4697e ) v th 50 150 mv see table 4 , figure 36 input hysteresis type 1 receiver ( adn4691e , adn4693e ) v hys 25 mv type 2 receiver ( adn4696e , adn4697e ) v hys 0 mv differential input voltage magnitude |v id | 0.05 v cc v input capacitance c a or c b 3 pf v i = 0.4 sin(30e 6 t) v + 0.5 v, 2 other input = 1.2 v differential input capacitance c ab 2.5 pf v ab = 0.4 sin(30e 6 t) v 2 input capacitance balance (c a /c b ) c a/b 0.99 1.01 logic output ro output high voltage v oh 2.4 v i oh = C8 ma output low voltage v ol 0.4 v i ol = 8 ma high impedance output current i oz ?10 +15 a v o = 0 v or 3.6 v logic input re input high voltage v ih 2 v cc v input low voltage v il gnd 0.8 v input high current i ih ?10 0 a v ih = 2 v input low current i il ?10 0 a v il = 0.8 v
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 4 of 20 parameter symbol min typ max unit test conditions/comments bus input/output input current a (receiver or transceiver with driver disabled) i a 0 32 a v b = 1.2 v, v a = 3.8 v ?20 +20 a v b = 1.2 v, v a = 0 v or 2.4 v ?32 0 a v b = 1.2 v, v a = ?1.4 v b (receiver or transceiver with driver disabled) i b 0 32 a v a = 1.2 v, v b = 3.8 v ?20 +20 a v a = 1.2 v, v b = 0 v or 2.4 v ?32 0 a v a = 1.2 v, v b = ?1.4 v differential (receiver or transceiver with driver disabled) i ab ?4 +4 a v a = v b , 1.4 v v a 3.8 v power-off input current 0 v v cc 1.5 v a (receiver or transceiver) i a(off) 0 32 a v b = 1.2 v, v a = 3.8 v ?20 +20 a v b = 1.2 v, v a = 0 v or 2.4 v ?32 0 a v b = 1.2 v, v a = ?1.4 v b (receiver or transceiver) i b(off) 0 32 a v a = 1.2 v, v b = 3.8 v ?20 +20 a v a = 1.2 v, v b = 0 v or 2.4 v ?32 0 a v a = 1.2 v, v b = ?1.4 v differential (receiver or transceiver) i ab(off) ?4 +4 a v a = v b , 1.4 v a 3.8 v input capacitance (transceiver with driver disabled) c a or c b 5 pf v i = 0.4 sin(30e 6 t) v + 0.5 v, 2 other input = 1.2 v, de = 0 v differential input capacitance (transceiver with driver disabled) c ab 3 pf v ab = 0.4 sin(30e 6 t) v, 2 de = 0 v input capacitance balance (c a /c b ) (transceiver with driver disabled) c a/b 0.99 1.01 de = 0 v power supply supply current i cc only driver enabled 13 22 ma de, re = v cc , r l = 50 both driver and receiver disabled 1 4 ma de = 0 v, re = v cc , r l = no load both driver and receiver enabled 16 24 ma de = v cc , re = 0 v, r l = 50 only receiver enabled 4 13 ma de, re = 0 v, r l = 50 1 all typical values are given for v cc = 3.3 v and t a = 25c. 2 hp4194a impedance anal yzer (or equivalent). receiver input threshold test voltages re = 0 v, h = high, l = low table 3. test voltages for type 1 receiver applied voltages input voltage, differential input voltage, common mode receiver output v a (v) v b (v) v id (v) v ic (v) ro (v) 2.4 0 2.4 1.2 h 0 2.4 ?2.4 1.2 l 3.8 3.75 0.05 3.775 h 3.75 3.8 ?0.05 3.775 l ?1.35 ?1.4 0.05 ?1.375 h ?1.4 ?1.35 ?0.05 ?1.375 l
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 5 of 20 table 4. test voltages for type 2 receiver applied voltages input voltage, differential input voltage, common mode receiver output v a (v) v b (v) v id (v) v ic (v) ro (v) +2.4 0 +2.4 +1.2 h 0 +2.4 ?2.4 +1.2 l +3.8 +3.65 +0.15 +3.725 h +3.8 +3.75 +0.05 +3.775 l ?1.25 ?1.4 +0.15 ?1.325 h ?1.35 ?1.4 +0.05 ?1.375 l timing specifications v cc = 3.0 v to 3.6 v; t a = t min to t max , unless otherwise noted. 1 table 5. parameter symbol min typ max unit test conditions/comments driver maximum data rate 200 mbps propagation delay t plh , t phl 1 1.5 2.4 ns see figure 24 , figure 27 differential output rise/fall time t r , t f 1 1.6 ns see figure 24 , figure 27 pulse skew |t phl C t plh | t sk 0 100 ps see figure 24 , figure 27 part-to-part skew 2 t sk(pp) 1 ns see figure 24 , figure 27 period jitter, rms (1 standard deviation) 3 t j(per) 2 3 ps 100 mhz clock input 4 (see figure 26 ) peak-to-peak jitter 3 , 5 t j(pp) 30 130 ps 200 mbps 2 15 ? 1 prbs input 6 (see figure 29 ) disable time from high level t phz 7 ns see figure 25 , figure 28 disable time from low level t plz 7 ns see figure 25 , figure 28 enable time to high level t pzh 7 ns see figure 25 , figure 28 enable time to low level t pzl 7 ns see figure 25 , figure 28 receiver propagation delay t rplh , t rphl 2 4 6 ns c l = 15 pf (see figure 30 , figure 33 ) rise/fall time t r , t f 1 2.3 ns c l = 15 pf (see figure 30 , figure 33 ) pulse skew |t rphl C t rplh | t sk c l = 15 pf (see figure 30 , figure 33 ) type 1 receiver ( adn4691e , adn4693e ) 100 300 ps type 2 receiver ( adn4696e , adn4697e ) 300 500 ps part-to-part skew 2 t sk(pp) 1 ns c l = 15 pf (see figure 30 , figure 33 ) period jitter, rms (1 standard deviation) 3 t j(per) 4 7 ps 100 mhz clock input 7 (see figure 32 ) peak-to-peak jitter 3 , 5 t j(pp) 200 mbps 2 15 ? 1 prbs input 8 (see figure 35 ) type 1 receiver ( adn4691e , adn4693e ) t j(pp) 300 700 ps type 2 receiver ( adn4696e , adn4697e ) 450 800 ps disable time from high level t rphz 10 ns see figure 31 , figure 34 disable time from low level t rplz 10 ns see figure 31 , figure 34 enable time to high level t rpzh 15 ns see figure 31 , figure 34 enable time to low level t rpzl 15 ns see figure 31 , figure 34 1 all typical values are given for v cc = 3.3 v and t a = 25c. 2 t sk(pp) is defined as the difference between the propagation delays of two devices between any specifie d terminals. this specification applies to device s at the same v cc and temperature, and with identica l packages and test circuits. 3 jitter parameters are guaranteed by design and characterization. values do not include stimulus jitter. 4 t r = t f = 0.5 ns (10% to 90%), measured over 30,000 samples. 5 peak-to-peak jitter specifications include jitter due to pulse skew (t sk ). 6 t r = t f = 0.5 ns (10% to 90%), measured over 100,000 samples. 7 |v id | = 400 mv ( adn4696e , adn4697e ), v ic = 1.1 v, t r = t f = 0.5 ns (10% to 90%), measured over 30,000 samples. 8 |v id | = 400 mv ( adn4696e , adn4697e ), v ic = 1.1 v, t r = t f = 0.5 ns (10% to 90%), measured over 100,000 samples.
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 6 of 20 absolute maximum ratings t a = t min to t max , unless otherwise noted. thermal resistance table 6. parameter rating v cc ?0.5 v to +4 v digital input voltage (de, re , di) ?0.5 v to +4 v receiver input (a, b) voltage half-duplex ( adn4691e , adn4696e ) ?1.8 v to +4 v full-duplex ( adn4693e , adn4697e ) ?4 v to +6 v receiver output voltage (ro) ?0.3 v to +4 v driver output (a, b, y, z) voltage ?1.8 v to +4 v esd rating (a, b, y, z pins) hbm (human body model) air discharge 15 kv contact discharge 8 kv iec 61000-4-2, air discharge 10 kv iec 61000-4-2, contact discharge 8 kv esd rating (other pins, hbm) 4 kv esd rating (all pins) ficdm 1.25 kv machine model 400 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja unit 8-lead soic 121 c/w 14-lead soic 86 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 7 of 20 pin configurations and function descriptions ro 1 re 2 de 3 di 4 v cc 8 b 7 a 6 gnd 5 adn4691e/ adn4696e top view (not to scale) 10355-003 figure 3. adn4691e / adn4696e pin configuration nc 1 2 3 4 v cc 14 13 12 11 5 10 gnd 6 y 9 gnd 7 nc 8 nc = no connect adn4693e/ adn4697e top view (not to scale) ro re de di v cc a b z 10355-004 figure 4. adn4693e / adn4697e pin configuration table 8. pin function descriptions adn4691e / adn4696e pin no. adn4693e / adn4697e pin no. mnemonic description 1 2 ro receiver output. type 1 receiver ( adn4691e / adn4693e ), when enabled: if a ? b 50 mv, then ro = logic high. if a ? b ?50 mv, then ro = logic low. type 2 receiver ( adn4696e / adn4697e ), when enabled: if a ? b 150 mv, then ro = logic high. if a ? b 50 mv, then ro = logic low. receiver output is undefine d outside these conditions. 2 3 re receiver output enable. a logic low on this pin enables the receiver output, ro. a logic high on this pin places ro in a high impedance state. 3 4 de driver output enable. a logic high on this pin enables the driver differential outputs. a logic low on this pin places the driver diff erential outputs in a high impedance state. 4 5 di driver input. half-duplex ( adn4691e / adn4696e ), when enabled: a logic low on di forces a low and b high, whereas a logic high on di forces a high and b low. full-duplex ( adn4693e / adn4697e ), when enabled: a logic low on di forces y low and z high, whereas a logic high on di forces y high and z low. 5 6, 7 gnd ground. n/a 9 y noninverting driver output y. n/a 10 z inverting driver output z. 6 n/a a noninverting receiver input a and noninverting driver output a. n/a 12 a noninverting receiver input a. 7 n/a b inverting receiver input b and inverting driver output b. n/a 11 b inverting receiver input b. 8 13, 14 v cc power supply (3.3 v 0.3 v). n/a 1, 8 nc no connect. do not connect to these pins.
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 8 of 20 typical performance characteristics 0 2 4 6 8 10 12 14 16 18 20 0 20406080100120 supply current, i cc (ma) frequency (mhz) driver receiver (v id = 250mv, v ic = 1v) 10355-005 figure 5. power supply current (i cc ) vs. frequency (v cc = 3.3 v, t a = 25c; receiver v id = 250 mv, v ic = 1 v) 0 2 4 6 8 10 12 14 16 18 20 ?50 ?30 ?10 10 30 50 70 90 supply current, i cc (ma) temperature (c) driver receiver (v id = 250mv, v ic = 1v) 10355-006 figure 6. power supply current vs. temperature (data rate = 200 mbps, v cc = 3.3 v; receiver v id = 250 mv, v ic = 1 v) 0 5 10 15 20 25 30 35 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 receiver low level output current, i ol (ma) receiver low level output voltage, v ol (v) v cc =3v v cc =3.3v v cc =3.6v 10355-007 figure 7. receiver output current vs. output voltage (output low) (t a = 25c) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 receiver high level output current (ma) receiver high level output voltage, v oh (v) v cc = 3.0v v cc = 3.3v v cc = 3.6v 10355-008 figure 8. receiver output current vs. output voltage (output high) (t a = 25c) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 02468101214 differenti a l output vol t age, v od (v) output current, i o (ma) 10355-009 figure 9. driver differential output voltage vs. output current (v cc = 3.3 v, t a = 25c) 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 ?40 ?20 0 20 40 60 80 driver propagation delay (ns) temperature, t a (c) t plh t phl 10355-010 figure 10. driver propagation delay vs. temperature (data rate = 2 mbps, v cc = 3.3 v)
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 9 of 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?50 ?30 ?10 10 30 50 70 90 receiver propa g a tion del a y (ns) temperature, t a (c) t rplh t rphl 10355-011 figure 11. receiver propagation delay vs. temperature (data rate = 2 mbps, v cc = 3.3 v, v id = 400 mv, v ic = 1.1 v) 0 0.5 1.0 1.5 2.0 2.5 3.0 20 30 40 50 60 70 80 90 100 added driver period jitter (ps) frequency (mhz) 10355-012 figure 12. driver jitter (period) vs. frequency (v cc = 3.3 v, t a = 25c, clock input) 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 200 added driver peak-to-peak jitter (ps) data rate (mbps) 10355-013 figure 13. driver jitter (peak-to-peak) vs. data rate (v cc = 3.3 v, t a = 25c, prbs 2 15 ? 1 input) 0 20 40 60 80 100 120 ?50 ?30 ?10 10 30 50 70 90 added driver peak-to-peak jitter (ps) temperature, t a (c) 10355-014 figure 14. driver jitter (peak-to-peak) vs. temperature (data rate = 200 mbps, v cc = 3.3 v, prbs 2 15 ? 1 input) 0 1 2 3 4 5 6 7 0 20406080100120 added receiver period jitter (ps) frequency (mhz) 10355-015 figure 15. receiver jitter (period) vs. frequency (v cc = 3.3 v, t a = 25c, v id = 400 mv) 0 100 200 300 400 500 600 700 800 ?50 ?30 ?10 10 30 50 70 90 added receiver peak?to?peak jitter (ps) temperature (c) 10355-016 figure 16. receiver jitter (peak-to-peak) vs. temperature (data rate = 200 mbps, v cc = 3.3 v, v id = 400 mv, v ic = 1.1 v, prbs 2 15 ? 1 input)
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 10 of 20 10355-017 1ns/div 200mv/di v figure 17. adn4696e driver output eye pattern (data rate = 200 mbps, prbs 2 15 ? 1 input, r l = 50 ) 10355-018 2.5ns/div 500mv/di v figure 18. adn4696e receiver output eye pattern (data rate = 200 mbps, prbs 2 15 ? 1 input, c l = 15 pf)
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 11 of 20 test circuits and switching characteristics driver voltage and current measurements di notes 1. 1% tolerance for all resistors v od v test 49.9 ? 3.32k ? + ? 3.32k ? ?1v to +3.4v 10355-019 a/y b/z figure 19. driver voltage measurement over common-mode range di notes 1. c1, c2, and c3 are 20% and include probe/stray capacitance less than 2cm from dut. 2. r1 and r2 are 1%, metal film, surface mount, less than 2cm from dut. v oc r1 24.9 ? c1 1pf c2 1pf c3 2.5pf r2 24.9 ? 10355-020 a/y b/z figure 20. driver common-mode output voltage measurement s1 s2 v a(o) , v b(o) , v y(o) or v z(o) a/y v cc r1 1.62k ? 1% b/zde 10355-021 figure 21. maximum steady-state output voltage measurement s1 di s2 a/y b/z v test v cc i os ?1v or +3.4v 10355-022 figure 22. driver short circuit notes 1. input pulse generator: 500khz; 50% 5% dut y cycle; t r , t f 1ns. 2. v oc(pp) measured on test equipment with ?3db bandwidth 1ghz. v oc(pp) ? v oc(ss) v oc b/z a / y 0.7v 1.3v 10355-023 figure 23. driver common-mode output voltage (steady state)
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 12 of 20 driver timing measurements di notes 1. c1, c2, and c3 are 20% and include probe/stray capacitance less than 2cm from dut. 2. r1 is 1%, metal film, surface mount, less than 2cm from dut. out c1 1pf c3 0.5pf c2 1pf 10355-024 a/y b/z r1 50? figure 24. driver timing measurement di de s1 v cc notes 1. c1, c2, c3, and c4 are 20% and include probe/stray capacitance less than 2cm from dut. 2. r1 and r2 are 1%, metal film, surface mount, less than 2cm from dut. r1 24.9 ? c1 1pf c2 1pf c3 2.5pf r2 24.9 ? 10355-025 a/y b/z c4 0.5pf out figure 25. driver enable/disable time notes 1. input pulse generator: agilent 8304a stimulus system; 100mhz; 50% 1% duty cycle. 2. measured using tek tds6604 with tdsjit3 software. v cc /2 v cc /2 v cc 0v 1/f0 input (clock) 10355-026 0v 0v 1/f0 output v a ? v b or v y ? v z (ideal) 0v 0v t c(n) t j(per) = | t c(n) ? 1/f0| output v a ? v b or v y ? v z ( actu a l ) figure 26. driver period jitter characteristics notes 1. input pulse generator: 500khz; 50% 5% dut y cycle; t r , t f 1ns. 2. measured on test equipment with ?3db bandwidth 1ghz. t plh t r t f t phl v cc v ss v ph v pl 0% v ss 10% v ss 90% v ss 0v 0v 0v out di 10355-027 10% v ss 90% v ss 0.5v cc 0.5v cc figure 27. driver propagation, rise/fall times and voltage overshoot 0.5v cc 0.5v cc v cc 0v 0v 0v ~ ?0.6v ~ 0.6v ?0.1v 0.1v 0.1v de out (di = 0v) out (di = v cc ) 10355-028 t pzh t pzl ?0.1v t phz t plz notes 1. input pulse generator: 500khz; 50% 5% dut y cycle; t r , t f 1ns. 2. measured on test equipment with ?3db bandwidth 1ghz. figure 28. driver enable/disable times notes 1. input pulse generator: agilent 8304a stimulus system; 200mbps; 2 15 ? 1prbs. 2. measured using tek tds6604 with tdsjit3 software. v a ? v b or v y ? v z v a ? v b or v y ? v z v cc output input (prbs) 0v 0.5v cc t j(pp) 0v 0v 0.5v cc 10355-029 figure 29. driver peak-to-peak jitter characteristics
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 13 of 20 receiver timing measurements a notes 1. c l is 20%, ceramic, surface mount, and includes probe/stray capacitance < 2cm from dut. v out c l 15pf b 10355-030 ro re v id figure 30. receiver timing measurement a 1.4 v 1.0v 1.2v re input notes 1. c l is 20% and includes probe/stray capacitance < 2cm from dut. 2. r l is 1% metal film, surface mount, <2cm from dut. v out c l 15pf r l 499 ? b 10355-031 ro re v test figure 31. receiver enable/disable time notes 1. input pulse generator: agilent 8304a stimulus system; 100mhz; 50% 1% duty cycle. 2. measured using tek tds6604 with tdsjit3 software. v oh v ol 0v 1/f0 input (v a ? v b ) 10355-032 0.5v cc 0.5v cc 0.5v cc 0.5v cc 1/f0 output (ideal) v oh v ol output (actual) t c(n) t j(per) = | t c(n) ? 1f0| figure 32. receiver period jitter characteristics notes 1. input pulse generator: 50mhz; 50% 5% duty cycle; t r , t f 1ns. 2. measured on test equipment with ?3db bandwidth 1ghz. t rphl v a 0.5v cc 0.5v cc v b v oh v ol v id v out 0v 90% 10% 90% 10% 0v t f t rplh t r 10355-033 figure 33. receiver propagation and rise/fall times 0.5v cc 0.5v cc v cc 0v v cc 0v v ol v oh 0.5v cc 0.5v cc v oh ? 0.5v re input (v test = v cc ) (a = 1v) v out v out (v test = 0v) (a = 1.4v) 10355-034 t rpzh t rpzl v ol + 0.5v t rphz t rplz notes 1. input pulse generator: 500khz; 50% 5% dut y cycle; t r , t f 1ns. figure 34. receiver enable/disable times notes 1. input pulse generator: agilent 8304a stimulus system; 200mbps; 2 15 ? 1prbs. 2. measured using tek tds6604 with tdsjit3 software. v oh v ol v a v b output input (prbs) t j(pp) 0.5v cc 0.5v cc 10355-035 figure 35. receiver peak-to-peak jitter characteristics
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 14 of 20 theory of operation the adn4691e / adn4693e / adn4696e / adn4697e are transceivers for transmitting and receiving multipoint, low voltage differential signaling (m-lvds) at high speed (data rates up to 200 mbps). each device has a differential line driver and a differential line receiver, allowing each device to send and receive data. multipoint lvds expands on the established lvds low voltage differential signaling method by allowing bidirectional commu- nication between more than two nodes. up to 32 nodes can be connected on an m-lvds bus. half-duplex/full-duplex operation half-duplex operation allows a transceiver to transmit or receive, but not both at the same time. however, with full- duplex operation, a transceiver can transmit and receive simultaneously. the adn4691e / adn4696e are half-duplex devices in which the driver and the receiver share differential bus terminals. the adn4693e / adn4697e are full-duplex devices that have dedicated driver output and receiver input pins. figure 37 and figure 38 show typical half- and full-duplex bus topologies, respectively, for m-lvds. three-state bus connection the outputs of the device can be placed in a high impedance state by disabling the driver or receiver. this allows several driver outputs to be connected to a single m-lvds bus. note that, on each bus line, only one driver can be enabled at a time, but many receivers can be enabled at the same time. the driver can be enabled or disabled using the driver enable pin (de). de enables the driver outputs when taken high; when taken low, de puts the driver outputs into a high impedance state. similarly, an active low receiver enable pin ( re ) controls the receiver. taking re low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state. truth tables for driver and receiver output states under various conditions are shown in table 1 0 , table 11 , table 12 and table 13 . truth tables table 9. truth table abbreviations abbreviation description h high level l low level x dont care i indeterminate z high impedance (off ) nc disconnected driver, half duplex ( adn4691e / adn4696e ) table 10. transmitting (see table 9 for abbreviations) inputs outputs power de di a b yes h h h l yes h l l h yes h nc l h yes l x z z yes nc x z z 1.5 v x x z z driver, full duplex ( adn4693e / adn4697e ) table 11. transmitting (see table 9 for abbreviations) inputs outputs power de di y z yes h h h l yes h l l h yes h nc l h yes l x z z yes nc x z z 1.5 v x x z z type 1 receiver ( adn4691e/ adn4693e) table 12. receiving (see table 9 for abbreviations) inputs output power a ? b re ro yes 50 mv l h yes ?50 mv l l yes ?50 mv < a ? b < 50 mv l i yes nc l i yes x h z yes x nc z no x x z type 2 receiver ( adn4696e/ adn4697e) table 13. receiving (see table 9 for abbreviations) inputs output power a ? b re ro yes 150 mv l h yes 50 mv l l yes 50 mv < a ? b < 150 mv l i yes nc l l yes x h z yes x nc z no x x z
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 15 of 20 glitch-free power-up/power-down to minimize disruption to the bus when adding nodes, the m-lvds outputs of the device are kept glitch-free when the device is powering up or down. this feature allows insertion of devices onto a live m-lvds bus because the bus outputs are not switched on before the device is fully powered. in addition, all outputs are placed in a high impedance state when the device is powered off. fault conditions the adn4691e / adn4693e / adn4696e / adn4697e contain short-circuit current protection that protects the part under fault conditions in the case of short circuits on the bus. this protection limits the current in a fault condition to 24 ma at the transmitter outputs for short-circuit faults between ?1 v and +3.4 v. any network fault must be cleared to avoid data transmission errors and to ensure reliable operation of the data network and any devices that are connected to the network. receiver input thresholds/fail-safe two receiver types are available, both of which incorporate protection against short circuits. the type 1 receivers of the adn4691e/ adn4693e incorporate 25 mv of hysteresis. this ensures that slow-changing signals or a loss of input does not result in oscillation of the receiver output. type 1 receiver thresholds are 50 mv; therefore, the state of the receiver output is indeterminate if the differential between a and b is about 0 v. this state occurs if the bus is idle (approximately 0 v on both a and b), with no drivers enabled on the attached nodes. type 2 receivers ( adn4696e / adn4697e ) have an open circuit and bus-idle fail-safe. the input threshold is offset by 100 mv so that a logic low is present on the receiver output when the bus is idle or when the receiver inputs are open. the different receiver thresholds for the two receiver types are illustrated in figure 36 . see table 12 and table 13 for receiver output states under various conditions. type 1 receive r output logic 1 logic 0 differenti a l input voltage (v ia ? v ib ) [v] 0.25 0.15 0.05 ?0.05 ?0.15 0 type 2 receive r output logic 1 logic 0 undefined 10355-036 undefined figure 36. input threshold voltages
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 16 of 20 applications information m-lvds extends the low power, high speed, differential signaling of lvds (low voltage differential signaling) to multipoint systems where multiple nodes are connected over short distances in a bus topology network. with m-lvds, a transmitting node drives a differential signal across a transmission medium such as a twisted pair cable. the transmitted differential signal allows other receiving nodes that are connected along the bus to detect a differential voltage that can then be converted back into a single-ended logic signal by the receiver. the communication line is typically terminated at both ends by resistors (r t ), the value of which is chosen to match the characteristic impedance of the medium (typically 100 ). for half-duplex multipoint applications such as the one shown in figure 37 , only one driver can be enabled at any time. full- duplex nodes allow a master-slave topology as shown in figure 38 . in this configuration, a master node can concurrently send and receive data to/from slave nodes. at any time, only one slave node can have its driver enabled to concurrently transmit data back to the master node. ro notes 1. maximum number of nodes: 32. 2. r t is equal to the characteristic impedance of the cable used. re ab r d r t r t adn4696e de di ro re ab adn4696e de di ro re ab adn4696e de di ro re ab adn4696e de di 10355-037 r d r d r d r d r d r d r d figure 37. adn4696e typical half-duplex m-lvds network (type 2 receivers with threshold offset for bus-idle fail-safe) ro notes 1. maximum number of nodes: 32. 2. r t is equal to the characteristic impedance of the cable used. re abzy master slave slave slave r t r t adn4697e de di ro re de di ro re de di abzy adn4697e abzy adn4697e abzy adn4697e r t r t ro re de di 10355-038 r d r d r d r d figure 38. adn4697e typical full-duplex m-lvds master-slave network (type 2 receivers with threshold offset for bus-idle fail-safe)
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 17 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 39. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are ro unded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 40. 14-lead standard small outline package [soic_n] narrow body (r-14) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option adn4691ebrz C40c to +85c 8-lead standard small outline package (soic_n) r-8 adn4691ebrz-rl7 C40c to +85c 8-lead stan dard small outline package (soic_n) r-8 ADN4693EBRZ C40c to +85c 14-lead standard small outline package (soic_n) r-14 ADN4693EBRZ-rl7 C40c to +85c 14-lead standard small outline package (soic_n) r-14 adn4696ebrz C40c to +85c 8-lead standard small outline package (soic_n) r-8 adn4696ebrz-rl7 C40c to +85c 8-lead stan dard small outline package (soic_n) r-8 adn4697ebrz C40c to +85c 14-lead standard small outline package (soic_n) r-14 adn4697ebrz-rl7 C40c to +85c 14-lead standard small outline package (soic_n) r-14 eval-adn469xehdebz evaluation board for half-duplex (adn4691e/adn4696e) eval-adn469xefdebz evaluation board for full-duplex (adn4693e/adn4697e) 1 z = rohs compliant part.
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 18 of 20 notes
data sheet adn4691e/adn4693e/adn4696e/adn4697e rev. a | page 19 of 20 notes
adn4691e/adn4693e/adn4696e/adn4697e data sheet rev. a | page 20 of 20 notes ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10355-0-3/12(a)

▲Up To Search▲

Price & Availability of ADN4693EBRZ

	To Download ADN4693EBRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .